The invention relates to a circuit for generating a plurality of related timing signals, and particularly to such a circuit that does not require a high frequency clock signal from which the timing signals must be derived in order to obtain high resolution of edges of the timing signals.
All digital electronic systems require timing generator circuits to generate the various digital clock signals that are required to keep different digital elements synchronized. Such digital timing generator circuits generally include various connections of logic gates, flip-flops, digital delay elements, programmed logic arrays, and/or microprocessors. A problem is that all of the timing signals which are derived from such digital timing circuitry must be multiples of a "master" input clock frequency. Therefore, if high resolution is required for leading and/or trailing edges of timing signals generated by the prior timing generator circuits, very high frequency clock signals are required. Such high frequency clock signals, when they appear on printed circuit board conductors, couple noise onto other printed circuit board conductors. This may produce a need for electrical shielding that substantially increases the cost of the printed circuit board. Furthermore, it is difficult to transmit high frequency clock signals around a printed circuit board because various parasitic RC time constants associated therewith result in degrading the clock signal. Furthermore, master clock circuits for producing clock frequencies above 10-15 megahertz are expensive (the higher the frequency, the greater the expense), and clock frequencies greater than 15 megahertz may be needed for many applications. For example, at the present state of the CMOS technology, it is impractical or at least expensive and difficult to achieve internally generated timing signals with high accuracy. Another problem in typical circuits used to generate high accuracy, high speed timing pulse signals is that there may be substantial capacitive loading or other loading on the conductors supplying such signals, and such loading may significantly alter the accuracy of the timing signals.
U.S. Pat. No. 3,206,686 discloses a delay time controller including a variable delay line connected in a loop with a phase discriminator and an amplifier that form a phase-locked loop. However, this reference does not disclose multiple delay line outputs, and cannot be used to generate a plurality of related timing signals. U.S. Pat. No. 4,494,021 discloses a circuit including a delay line. A circuit is disclosed to generate a control voltage that drives the tapped delay line, and the delay of individual elements of the delay line are controlled. A phase locked loop circuit generates the control voltage, but the delay line is not included in the phase locked loop. Accuracy of the delay of individual delay elements in the delay line requires precise matching between a voltage controlled oscillator and the delay line to ensure that delay per cell is as desired.